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electrical specifications subject to change ltc6990 1 6990p typical application description timerblox: voltage controlled silicon oscillator the ltc ? 6990 is a precision silicon oscillator with a pro- grammable frequency range of 488hz to 2mhz. it can be used as a ? xed-frequency or voltage-controlled oscillator (vco). the ltc6990 is part of the timerblox? family of versatile silicon timing devices. a single resistor, r set , programs the ltc6990s inter- nal master oscillator frequency. the output frequency is determined by this master oscillator and an internal frequency divider, n div , programmable to eight settings from 1 to 128. f out = 1mhz n div ? 50k r set ,n div = 1, 2, 4 ?128 optionally, a second resistor at the set input provides linear voltage control of the output frequency and can be used for frequency modulation. a narrow or wide vco tuning range can be con? gured by the appropriate selection of the two resistors. the ltc6990 includes an enable function that is synchro- nized with the master oscillator to ensure clean, glitch-free output pulses. the disabled output can be con? gured to be high impedance or forced low. the ltc6990 is available in the 6-lead sot-23 (thinsot) package or a 6-lead 2mm 3mm dfn. voltage controlled oscillator with 16:1 frequency range l , lt, ltc and ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. timerblox and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6342817, 6614313. features applications n fixed-frequency or voltage-controlled operation C fixed: single resistor programs frequency with <2.2% max error C vco: two resistors set vco center frequency and tuning range n frequency range: 488hz to 2mhz n 2.25v to 5.5v single supply operation n 72a supply current at 100khz n 500s start-up time n vco bandwidth >300khz at 1mhz n cmos logic output sources/sinks 20ma n 50% duty cycle square wave output n output enable (selectable low or hi-z when disabled) n C40c to 125c operating temperature range n available in low pro? le (1mm) sot-23 (thinsot?) and 2mm 3mm dfn package n low cost precision programmable oscillator n voltage-controlled oscillator n high vibration, high acceleration environments n replacement for fixed crystal and ceramic oscillators n portable and battery-powered equipment vco transfer function v ctrl (v) 0 f out (khz) 1000 750 250 500 0 0.5 6990 ta01b 2 1 1.5 6990 ta01a ltc6990 oe gnd set out v + div c1 0.1f r set 100k v + v + v ctrl r vco 100k f out 1mhz v ctrl ? 0.5 mhz v
ltc6990 2 6990p absolute maximum ratings supply voltage (v + ) to gnd ........................................6v maximum voltage on any pin ............................. (gnd C 0.3v) v pin (v + + 0.3v) operating temperature range (note 2) ltc6990c ............................................C40c to 85c ltc6990i .............................................C40c to 85c ltc6990h .......................................... C40c to 125c (note 1) top view out gnd oe v + div set dcb package 6-lead (2mm 3mm) plastic dfn 4 5 7 6 3 2 1 t jmax = 150c, ja = 64c/w exposed pad (pin 7) connected to gnd, pcb connection optional oe 1 gnd 2 set 3 6 out 5 v + 4 div top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 230c/w pin configuration order information lead free finish tape and reel part marking* package description specified temperature range ltc6990cdcb#pbf ltc6990cdcb#trpbf ldwx 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6990idcb#pbf ltc6990idcb#trpbf ldwx 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6990hdcb#pbf ltc6990hdcb#trpbf ldwx 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6990cs6#pbf ltc6990cs6#trpbf ltdww 6-lead plastic tsot-23 0c to 70c ltc6990is6#pbf ltc6990is6#trpbf ltdww 6-lead plastic tsot-23 C40c to 85c ltc6990hs6#pbf ltc6990hs6#trpbf ltdww 6-lead plastic tsot-23 C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ speci? ed temperature range (note 3) ltc6990c ................................................ 0c to 70c ltc6990i .............................................C40c to 85c ltc6990h .......................................... C40c to 125c junction temperature ........................................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10sec) ................... 300c
ltc6990 3 6990p electrical characteristics symbol parameter conditions min typ max units f out output frequency recommended range: r set = 50k to 800k extended range: r set = 25k to 800k 0.488 0.488 1000 2000 khz khz f out frequency accuracy (note 4) recommended range r set = 50k to 800k l 0.8 1.5 2.2 % % extended range r set = 25k to 800k l 2.4 3.2 % % f out / t frequency drift over temperature l 0.005 %/c f out / v + frequency drift over supply v + = 4.5v to 5.5v v + = 2.25v to 4.5v l l 0.23 0.06 0.55 0.16 %/v %/v period jitter (note 10) n div = 1 0.38 % p-p n div = 2 0.22 0.027 % p-p % rms n div = 128 0.022 0.004 % p-p % rms duty cycle n div = 1, r set = 25k to 800k n div > 1, r set = 25k to 800k l l 47 48 50 50 53 52 % % bw frequency modulation bandwidth 0.4?f out khz t s frequency change settling time (note 9) t master = t out /n div 6?t master s analog inputs v set voltage at set pin l 0.97 1.00 1.03 v v set / t v set drift over temperature l 75 v/c v set / v + v set drift over supply C150 v/v v set / i set v set droop with i set C7 r set frequency-setting resistor recommended range extended range l l 50 25 800 800 k k v div div pin voltage l 0v + v v div /v + div pin valid code range (note 5) deviation from ideal v div /v + = (divcode + 0.5)/16 l 1.5 % div pin input current l 10 na power supply v + operating supply voltage range l 2.25 5.5 v power-on reset voltage r set = 25k to 800k l 1.95 v i s supply current r l = , n div = 1, r set = 50k v + = 5.5v v + = 2.25v l l 235 145 283 183 a a r l = , n div = 1 r set = 800k v + = 5.5v v + = 2.25v l l 71 59 105 92 a a r l = , n div = 128, r set = 50k v + = 5.5v v + = 2.25v l l 137 106 180 145 a a r l = , n div = 128, r set = 800k v + = 5.5v v + = 2.25v l l 66 56 100 90 a a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 2.25v to 5.5v, oe = v + , divcode = 0 to 15 (n div = 1 to 128), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted.
ltc6990 4 6990p electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 2.25v to 5.5v, oe = v + , divcode = 0 to 15 (n div = 1 to 128), r set = 25k to 800k, r load = , c load = 5pf unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6990c is guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6990c is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6990c is designed, characterized and expected to meet speci? ed performance from C40c to 85c but it is not tested or qa sampled at these temperatures. the ltc6990i is guaranteed to meet speci? ed performance from C40c to 85c. the ltc6990h is guaranteed to meet speci? ed performance from C40c to 125c. note 4: frequency accuracy is de? ned as the deviation from the f out equation, assuming r set is used to program the frequency. note 5: see operation section, table 1 and figure 2 for a full explanation of how the div pin voltage selects the value of divcode. note 6: the oe pin has hysteresis to accommodate slow rising or falling signals. the threshold voltages are proportional to v + . typical values can be estimated at any supply voltage using v oe(rising) 0.55 ? v + + 185mv and v oe(falling) 0.48 ? v + C 155mv. note 7: to conform to the logic ic standard, current out of a pin is arbitrarily given a negative value. note 8: output rise and fall times are measured between the 10% and the 90% power supply levels with 5pf output load. these speci? cations are based on characterization. note 9: settling time is the amount of time required for the output to settle within 1% of the ? nal frequency after a 0.5x or 2x change in i set . note 10: jitter is the ratio of the deviation of the period to the mean of the period. this speci? cation is based on characterization and is not 100% tested. symbol parameter conditions min typ max units digital i/o oe pin input capacitance 2.5 pf oe pin input current oe = 0v to v + l 10 na v ih high level oe pin input voltage (note 6) l 0.7 ? v + v v il low level oe pin input voltage (note 6) l 0.3?v + v out pin hi-z leakage oe = 0v, divcode 8, out = 0v to v + 10 a i out(max) maximum output current 20 ma v oh high level output voltage (note 7) v + = 5.5v i oh = C1ma i oh = C16ma l l 5.45 4.84 5.48 5.15 v v v + = 3.3v i oh = C1ma i oh = C10ma l l 3.24 2.75 3.27 2.99 v v v + = 2.25v i oh = C1ma i oh = C8ma l l 2.17 1.58 2.21 1.88 v v v ol low level output voltage (note 7) v + = 5.5v i ol = 1ma i ol = 16ma l l 0.02 0.26 0.04 0.54 v v v + = 3.3v i ol = 1ma i ol = 10ma l l 0.03 0.22 0.05 0.46 v v v + = 2.25v i ol = 1ma i ol = 8ma l l 0.03 0.26 0.07 0.54 v v t pd output disable propagation delay v + = 5.5v v + = 3.3v v + = 2.25v 17 26 44 ns ns ns t enable output enable time n div 2, t out = 1/f out n div 4, t master = t out /n div t pd to t out t pd to 2? t master s s t r output rise time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.1 1.7 2.7 ns ns ns t f output fall time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.0 1.6 2.4 ns ns ns
ltc6990 5 6990p typical performance characteristics v set vs i set v set vs supply voltage v set vs temperature frequency error vs r set frequency error vs supply voltage frequency error vs temperature v + = 3.3v, unless otherwise noted. r set (k) frequency error (%) 6990 g01 4 3 2 1 C1 C2 C3 0 C4 10 100 1000 t a = 25c guaranteed max over temperature guaranteed min over temperature typical max 90% of units typical min supply voltage (v) frequency error (%) 6990 g02 0.5 0.4 0.3 0.1 0.2 C0.1 C0.2 C0.3 0 C0.5 C0.4 24 356 t a = 25c r set = 800k r set = 200k r set = 50k i set (a) v set (v) 6990 g04 1.003 1.002 1.001 1.000 020 10 30 40 v + = 3.3v t a = 25c supply voltage (v) v set (v) 6990 g05 1.003 1.002 1.001 1.000 24 356 r set = 200k t a = 25c temperature (c) v set (v) 6990 g06 1.020 1.005 1.000 1.010 1.015 0.995 0.990 0.985 0.980 C50 75 50 025 C25 100 125 r set = 200k 3 typical parts temperature (c) error (%) 6990 g03 1.5 0.5 1.0 0.0 C0.5 C1.0 C1.5 C50 C25 25 50 0 100 75 125 v + = 3.3v divcode = 4 r set = 50k r set = 267k r set = 800k typical v set distribution supply current vs supply voltage supply current vs temperature v set (v) number of units 6990 g07 300 150 100 200 250 50 0 0.986 1.002 0.994 1.010 1.018 t a = 25c 2 lots dfn and sot-23 1416 units supply voltage (v) power supply current (a) 6990 g05 250 150 100 50 200 0 24 356 t a = 25c r set = 800k, 1 r set = 800k, 128 r set = 50k, 1 r set = 50k, 2 r set = 50k, 128 temperature (c) power supply current (a) 6990 g09 250 100 50 150 200 0 C50 75 50 025 C25 100 125 5.5v, r set = 800k, 1 2.25v, r set = 800k, 128 5.5v, r set = 50k, 1 2.25v, r set = 50k, 1 5.5v, r set = 50k, 128
ltc6990 6 6990p typical performance characteristics peak-to-peak jitter vs frequency oe threshold voltage vs supply voltage supply current vs frequency, 5v supply current vs frequency, 2.5v supply current vs oe pin voltage v + = 3v, unless otherwise noted. output resistance vs supply voltage frequency (khz) power supply currnet (a) 6990 g10 400 300 350 200 250 150 100 50 0 0.1 1 1000 10000 100 10 v + = 5v t a = 25c 128 1 2 recommended range extended range frequency (khz) power supply currnet (a) 6990 g11 400 300 350 200 250 150 100 50 0 0.1 1 1000 10000 100 10 v + = 2.5v t a = 25c recommended range extended range 128 1 2 v oe /v + (%) power supply current (a) 6990 g12 200 100 125 75 150 175 50 060 40 20 80 100 5v, oe rising t a = 25c r set = 800k divcode = 7 5v, oe falling 3.3v, oe rising 3.3v, oe falling supply voltage (v) oe pin voltage (v) 6990 g14 3.5 1.0 2.0 3.0 0.5 1.5 2.5 0 24 356 t a = 25c positive-going negative-going supply voltage (v) output resistance () 6990 g16 50 25 20 35 45 5 10 15 30 40 0 24 356 t a = 25c output sourcing current output sinking current frequency (khz) jitter (% p-p ) 6990 g13 0.50 0.25 0.30 0.40 0.20 0.10 0.05 0.15 0.35 0.45 0 0.1 10 100 1 1000 t a = 25c v + = 5v peak-to-peak period deviation measured over 30sec intervals 1 2 4 128
ltc6990 7 6990p rise and fall time vs supply voltage output disable propagation delay (t pd ) vs supply voltage typical performance characteristics frequency modulation frequency modulation typical i set current limit vs v + typical output waveform supply voltage (v) rise/fall time (ns) 6990 g16 3.0 1.5 2.5 1.0 0.5 2.0 0 24 356 t a = 25c c load = 5pf t rise t fall supply voltage (v) propagation delay (ns) 6990 g17 50 20 40 10 30 25 45 15 5 35 0 24 356 t a = 25c c load = 5pf supply voltage (v) i set (a) 6990 g18 1000 400 800 200 600 0 24 356 t a = 25c set pin shorted to gnd 20s/div 6990 g19 out 2v/div oe 2v/div v + = 3.3v divcode = 2 r set = 200k 20s/div 6990 g20 out 2v/div v ctrl 2v/div f out 50khz/div v + = 3.3v, divcode = 0 r set = 200k, r vco = 464k f out = 175khz to 350khz 20s/div 6990 g21 out 2v/div v ctrl 2v/div f out 50khz/div v + = 3.3v, divcode = 0 r set = 200k, r vco = 464k f out = 175khz to 350khz v + = 3v, unless otherwise noted.
ltc6990 8 6990p pin functions v + (pin 1/pin 5): supply voltage (2.25v to 5.5v). this sup- ply must be kept free from noise and ripple. it should be bypassed directly to the gnd pin with a 0.1f capacitor. div (pin 2/pin 4): programmable divider and hi-z mode input. a v + referenced a/d converter monitors the div pin voltage (v div ) to determine a 4-bit result (divcode). v div may be generated by a resistor divider between v + and gnd. use 1% resistors to ensure an accurate result. the div pin and resistors should be shielded from the out pin or any other traces that have fast edges. limit the capacitance on the div pin to less than 100pf so that v div settles quickly. the msb of divcode (hi-z) deter- mines the behavior of the output when oe is driven low. if hi-z = 0 the output is pulled low when disabled. if hi-z = 1 the output is placed in a high impedance condition when disabled. set (pin 3/pin 3): frequency-setting input. the voltage on the set pin (v set ) is regulated to 1v above gnd. the amount of current sourced from the set pin (i set ) pro- grams the master oscillator frequency. the i set current range is 1.25a to 40a. the output oscillation will stop if i set drops below approximately 500na. a resistor con- nected between set and gnd is the most accurate way to set the frequency. for best performance, use a precision metal or thin ? lm resistor of 0.5% or better tolerance and 50ppm/c or better temperature coef? cient. for lower ac- curacy applications an inexpensive 1% thick ? lm resistor may be used. limit the capacitance on the set pin to less than 10pf to minimize jitter and ensure stability. capacitance less than 100pf maintains the stability of the feedback circuit regulating the v set voltage. (dcb/s6) 6990 pf ltc6990 oe gnd set out v + div c1 0.1f r set r2 r1 v + v + oe (pin 4/pin 1): output enable. drive high to enable the output driver (pin 6). driving oe low disables the output asynchronously, so that the output is immediately forced low (hi-z = 0) or ? oated (hi-z = 1). when enabled, the output may temporarily remain low to synchronize with the internal oscillator in order to eliminate pulse slivers. gnd (pin 5/pin 2): ground. tie to a low inductance ground plane for best performance. out (pin 6/pin 6): oscillator output. the out pin swings from gnd to v + with an output resistance of approximately 30. when driving an led or other low-impedance load a series output resistor should be used to limit source/sink current to 20ma.
ltc6990 9 6990p block diagram 6990 bd programmable divider 1, 2, 4, 8, 16, 32, 64, 128 master oscillator hi-z when disabled hi-z output until settled por digital filter 4-bit a/d converter hi-z bit r1 r2 div v + oe out 5 4 1 6 halt oscillator if i set < 500na mclk + C i set v set = 1v + C 1v 3 2 2 gnd set r set t out t master 1 s 50k 7 ? v set i set (s6 package pin numbers shown)
ltc6990 10 6990p operation the ltc6990 is built around a master oscillator with a 1mhz maximum frequency. the oscillator is controlled by the set pin current (i set ) and voltage (v set ), with a 1mhz ? 50k conversion factor that is accurate to 0.8% under typical conditions. f master = 1 t master = 1mhz ? 50k ? i set v set a feedback loop maintains v set at 1v 30mv, leaving i set as the primary means of controlling the output frequency. the simplest way to generate i set is to connect a resistor (r set ) between set and gnd, such that i set = v set /r set . the master oscillator equation reduces to: f master = 1 t master = 1mhz ? 50k r set from this equation it is clear that v set drift will not affect the output frequency when using a single program resistor (r set ). error sources are limited to r set tolerance and the inherent frequency accuracy f out of the ltc6990. r set values between 50k and 800k (equivalent to i set between 1.25a and 20a) produce the best results, although r set may be reduced to 25k (i set = 40a) with reduced accuracy. the ltc6990 includes a programmable frequency divider which can further divide the frequency by 1, 2, 4, 8, 16, 32, 64 or 128 before driving the out pin. the divider ratio n div is set by a resistor divider attached to the div pin. f out = 1 t out = 1mhz ? 50k n div ? i set v set with r set in place of v set /i set the equation reduces to: f out = 1 t out = 1mhz ? 50k n div ?r set divcode the div pin connects to an internal, v + referenced 4-bit a/d converter that monitors the div pin voltage (v div ) to determine the divcode value. divcode programs two settings on the ltc6990: 1. divcode determines the output frequency divider setting, n div . 2. divcode determines the state of the output when disabled, via the hi-z bit. v div may be generated by a resistor divider between v + and gnd as shown in figure 1. figure 1. simple technique for setting divcode 6990 f01 ltc6990 v + div gnd r1 r2 2.25v to 5.5v
ltc6990 11 6990p table 1. divcode programming divcode hi-z n div recommended f out r1 (k) r2 (k) v div /v + 0 0 1 62.5khz to 1mhz open short 0.03125 0.015 1 0 2 31.25khz to 500khz 976 102 0.09375 0.015 2 0 4 15.63khz to 250khz 976 182 0.15625 0.015 3 0 8 7.813khz to 125khz 1000 280 0.21875 0.015 4 0 16 3.906khz to 62.5khz 1000 392 0.28125 0.015 5 0 32 1.953khz to 31.25khz 1000 523 0.34375 0.015 6 0 64 976.6hz to 15.63khz 1000 681 0.40625 0.015 7 0 128 488.3hz to 7.813khz 1000 887 0.46875 0.015 8 1 128 488.3hz to 7.813khz 887 1000 0.53125 0.015 9 1 64 976.6hz to 15.63khz 681 1000 0.59375 0.015 10 1 32 1.953khz to 31.25khz 523 1000 0.65625 0.015 11 1 16 3.906khz to 62.5khz 392 1000 0.71875 0.015 12 1 8 7.813khz to 125khz 280 1000 0.78125 0.015 13 1 4 15.63khz to 250khz 182 976 0.84375 0.015 14 1 2 31.25khz to 500khz 102 976 0.90625 0.015 15 1 1 62.5khz to 1mhz short open 0.96875 0.015 operation table 1 offers recommended 1% resistor values that ac- curately produce the correct voltage division as well as the corresponding n div and hi-z values for the recommended resistor pairs. other values may be used as long as: 1. the v div /v + ratio is accurate to 1.5% (including resis- tor tolerances and temperature effects) 2. the driving impedance (r1||r2) does not exceed 500k. if the voltage is generated by other means (i.e. the output of a dac) it must track the v + supply voltage. the last column in table 1 shows the ideal ratio of v div to the supply voltage, which can also be calculated as: v div v + = divcode + 0.5 16 1.5% for example, if the supply is 3.3v and the desired divcode is 4, v div = 0.281 ? 3.3v = 928mv 50mv. figure 2 illustrates the information in table 1, showing that n div is symmetric around the divcode midpoint. 0.5?v + f out (khz) 6990 f02 1000 100 10 1 0.1 increasing v div v + 0v recommended range extended range hi-z bit = 0 hi-z bit = 1 0 15 1 3 2 5 4 7 6 9 8 11 10 13 12 14 figure 2. frequency range and hi-z bit vs divcode
ltc6990 12 6990p operation on start-up, the div pin a/d converter must determine the correct divcode before the output is enabled. if v div is not stable, it will increase the start-up time as the converter waits for a stable result. therefore, capacitance on the div pin should be minimized so it will settle quickly. less than 100pf will not affect performance. output enable the oe pin controls the state of the ltc6990s output as seen on the out pin. pulling the oe pin high enables the oscillator output. pulling it low disables the output. when the output is disabled, it is either held low or placed in a high impedance state as dictated by the hi-z bit value (determined by the divcode as described earlier). table 2 summarizes the output control states. table 2. output states oe pin hi-z out 1 x enabled, output is active 0 1 disabled, output is hi-z 0 0 disabled, output is held low figure 3 illustrates the timing for the oe function when hi-z = 0. when oe is low, the output is disabled and out is held low. bringing oe high enables the output after a delay, t enable , which synchronizes the enable to eliminate sliver pulses and guarantee the correct width for the ? rst pulse. if n div = 1 or 2 this delay will be no longer than the output period, t out . if n div > 2 the delay is limited to twice the internal master oscillator period (or 2 ? t master ). forcing oe low will bring out low after a propagation delay, t pd . if the output is high when oe falls, the output pulse will be truncated. as shown in figure 4, setting hi-z = 1 places the output in a high-impedance state when oe = 0. this feature allows for wired-or connections of multiple devices. driving oe high enables the output. the output will usually be forced low during this time, although it is possible for out to transition directly from high-impedance to a high output, depending on the timing of the oe transition relative to the internal oscillator. once high, the ? rst output pulse will have the correct width (unless truncated by bringing oe low again). figure 3. oe timing diagram (hi-z = 0) 6990 f03 oe out t pd t pd t enable t enable t out figure 4. oe timing diagram (hi-z = 1) 6990 f04 oe out t pd t pd t pd t pd t enable t enable t out hi-z
ltc6990 13 6990p operation changing divcode after start-up following start-up, the a/d converter will continue monitoring v div for changes. changes to divcode will be recognized slowly, as the ltc6990 places a priority on eliminating any wandering in the divcode. the typical delay depends on the difference between the old and new divcode settings and is proportional to the master oscillator period. t divcode = 16 ? ( divcode + 6) ? t master a change in divcode will not be recognized until it is stable, and will not pass through intermediate codes. a digital ? lter is used to guarantee the divcode has settled to a new value before making changes to the output. then the output will make a clean (glitchless) transition to the new divider setting. start-up time when power is ? rst applied to the ltc6990 the power-on reset (por) circuit will initiate the start-up time, t start . the out pin is ? oated (high-impedance) during this time. the typical value for t start ranges from 0.5ms to 8ms depending on the master oscillator frequency (indepen- dent of n div ): t start(typ) = 500 ? t master the start-up time may be longer if the supply or div pin voltages are not stable. for this reason, it is recom- mended to minimize the capacitance on the div pin so it will properly track v + . figure 5. divcode change from 5 to 2 figure 6. typical start-up 100s/div 6990 f05 div 1v/div out 1v/div v + = 3.3v r set = 200k 576s 100s/div 6990 f06 v + 1v/div out 1v/div v + = 2.5v divcode = 4 r set = 50k output connected to 1.25v through 25k to show hi-z 470s
ltc6990 14 6990p applications information figure 7. start-up timing diagram (oe = 1, n div = 1 or 2, hi-z = 0 or 1) figure 8. start-up timing diagram (oe = 1, n div 4, hi-z = 0 or 1) figure 9. start-up timing diagram (oe = 0, n div = any, hi-z = 0) figure 10. start-up timing diagram (oe = 0, n div = any, hi-z = 1) 6990 f07 oe out 1/2 t out t out t start hi-z 6990 f08 oe out t out t master t start hi-z 6990 f09 oe out t out t enable t start hi-z 6990 f10 oe out t out t enable t start hi-z t pd remains hi-z until oe = 1
ltc6990 15 6990p applications information start-up behavior when ? rst powered up, the output is high impedance. if the output is enabled (oe = 1) at the end of the start-up time, the output will go low for one t master cycle (or half a t out cycle if n div < 4) before the ? rst rising edge. if the output is disabled (oe = 0) at the end of the start-up time, the output will drop to a low output if the hi-z bit = 0, or simply remain ? oating if hi-z = 1. basic fixed frequency operation the simplest and most accurate method to program the ltc6990 for ? xed frequency operation is to use a single resistor, r set , between the set and gnd pins. the design procedure is a simple two step process. first select the n div value and then calculate the value for the r set resistor. step 1: selecting the n div frequency divider value as explained earlier, the voltage on the div pin sets the divcode which determines both the hi-z bit and the n div value. for a given output frequency, n div should be selected to be within the following range. 62.5khz f out n div 1mhz f out (1a) to minimize supply current, choose the lowest n div value (generally recommended). for faster start-up or decreased jitter, choose a higher n div setting. alternatively, use table 1 as a guide to select the best n div value for the given ap- plication. after choosing the value for n div , use table 1 to select the proper resistor divider or v div /v + ratio to apply to the div pin. step 2: calculate and select r set the ? nal step is to calculate the correct value for r set using the following equation. r set = 1mhz ? 5 0k n div ?f out (1b) select the standard resistor value closest to the calculated value. example: design a 20khz oscillator with minimum power consumption step 1: selecting the n div frequency divider value first, choose an n div value that meets the requirements of equation (1a). 3.125 n div 50 potential settings for n div include 4, 8, 16, and 32. n div = 4 is the best choice, as it minimizes supply current by using a large r set resistor. using table 1, choose the r1 and r2 values to program divcode to either 2 or 13, depending on the desired behavior when the output is disabled. step 2: select r set calculate the correct value for r set using equation (1b). r set = 1mhz ? 5 0k 4 ? 20khz = 625k since 625k is not available as a standard 1% resistor, substitute 619k if a 0.97% frequency shift is acceptable. otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. frequency modulated operation (voltage-controlled oscillator) operating the ltc6990 as a voltage-controlled oscillator in its simplest form is achieved with one additional resistor. as shown in figure 11, voltage v ctrl sources/sinks a current through r vco to vary the i set current, which in turn modu- lates the output frequency as described in equation (2). f out = 1mhz ? 50k n div ?r vco ?1 + r vco r set ? v ctrl v set ? ? ? ? ? ? (2) figure 11. voltage controlled oscillator 6990 f08 ltc6990 oe gnd set out v + div c1 0.1f r1 r2 r set v + v + r vco v ctrl
ltc6990 16 6990p applications information equation (2) can be re-written as shown below, where f (0v) is the output frequency when v ctrl = 0v, and k vco is the frequency gain. note that the gain is negative (the output frequency decreases as v ctrl increases). f out = f (0v) ? k vco ? v ctrl f (0v) = 1mhz ? 50k n div ?r set p r vco ( ) k vco = 1mhz ? 5 0k n div ?v set ?r vco the design procedure for a vco is a simple four step process. first select the n div value. then calculate the intermediate values k vco and f (0v) . next, calculate and select the r vco resistor. finally calculate and select the r set resistor. step 1: select the n div frequency divider value for best accuracy, the master oscillator frequency should fall between 62.5khz and 1mhz. since f master = n div ? f out , choose a value for n div that meets the following conditions 62.5khz f out(min) n div 1mhz f out(max) (3a) the 16:1 frequency range of the master oscillator and the 2:1 divider step-size provides several overlapping fre- quency spans to guarantee that any 8:1 modulation range can be covered by a single n div setting. r vco allows the gain to be tailored to the application, mapping the v ctrl voltage range to the modulation range. step 2: calculate k vco and f (0v) k vco and f (0v) de? ne the vcos transfer function and simplify the calculation of the the r vco and r set resis- tors. calculate these parameters using the following equations. k vco = f out(max) ? f out(min) v ctrl(max) ? v ctrl(min) (3b) f (0v) = f out(max ) + k vco ? v ctrl(min) (3c) k vco and f (0v) are not device settings or resistor values themselves. however, beyond their utility for the resistor calculations, these parameters provide a useful and intuitive way to look at the vco application. the f (0v) parameter is the output frequency when v ctrl is at 0v. viewed another way, it is the ? xed output frequency when the r vco and r set resistors are in parallel. k vco is actually the frequency gain of the circuit. with k vco and f (0v) determined, the r vco and r set values can now be calculated. step 3: calculate and select r vco the next step is to calculate the correct value for r vco using the following equation. r vco = 1mhz ? 5 0k n div ?v set ?k vco (3d) select the standard resistor value closest to the calculated value. step 4: calculate and select r set the ? nal step is to calculate the correct value for r set using the following equation: r set = 1mhz ? 50k n div ?f (0v) ? v set ?k vco ( ) (3e) select the standard resistor value closest to the calculated value. some applications require combinations of f out(min) , f out(max) , v ctrl(min) and v ctrl(max) that are not achiev- able. these applications result in unrealistic or unrealiz- able (e.g. negative value) resistors. these applications will require preconditioning of the v ctrl signal via range scaling and/or level shifting to place the v ctrl into a range that yields realistic resistor values. frequency error in vco applications due to v set error as stated earlier, f (0v) represents the frequency for v ctrl = 0v, which is the same value as would be generated by a single resistor between set and gnd with a value of r set || r vco . therefore, f (0v) is not affected by error or drift in v set (i.e. v set adds no frequency error when v ctrl = 0v).
ltc6990 17 6990p figure 12. vco transfer function v ctrl (v) 1 f out (khz) 100 80 40 20 60 0 2 6990 f12 4 3 applications information the accuracy of k vco does depend on v set because the output frequency is controlled by the ratio of v ctrl to v set . the frequency error (in hertz) due to v set is ap- proximated by: f out ? k vco ?v ctrl ? v set v set as the equation indicates, the potential for error in output frequency due to v set error increases with k vco and is at its largest when v ctrl is at its maximum. recall that when v ctrl is at its maximum, the output frequency is at its minimum. with the maximum absolute frequency error (in hertz) occurring at the lowest output frequency, the relative frequency error (in percent) can be signi? cant. v set is nominally 1.0v with a maximum error of 30mv for at most a 3% error term. however, this 3% potential error term is multiplied by both v ctrl and k vco . wide fre- quency range applications (high k vco ) can have frequency errors greater than 50% at the highest v ctrl voltage (lowest f out ). for this reason the simple, two resistor vco circuit must be used with caution for applications where the frequency range is greater than 4:1. restricting the range to 4:1 typically keeps the frequency error due to v set variation below 10%. for wide frequency range applications, the non-inverting vco circuit shown in figure 13 is preferred because the maximum frequency error occurs when the frequency is highest, keeping the relative error (in percent) much smaller. example: design a vco with the following parameters f out(max) = 100khz at v ctrl(min) = 1v f out(min) = 10khz at v ctrl(max) = 4v step 1: select the n div value first, choose an n div that meets the requirements of equation (3a). 6.25 n div 10 the applications desired frequency range is 10:1, which isnt always possible. however, in this case n div = 8 meets both requirements of equation (3). step 2: calculate k vco and f (0v) next, calculate the intermediate values k vco and f (0v) using equations (3b) and (3c). k vco = 100khz ? 10khz 4v ? 1v = 30khz/v f (0v) = 100khz + 30khz/v ? 1v = 130khz step 3: calculate and select r vco the next step is to use equation (3d) to calculate the cor- rect value for r vco . r vco = 1mhz ? 5 0k 8?1v?30khz/v = 208.333k select r vco = 210k. step 4: calculate and select r set the ? nal step is to calculate the correct value for r set using equation (3e). r set = 1mhz ? 5 0k 8 ? 130khz ? 1v ? 3 0k h z/ v ( ) = 62.5k select r set = 61.9k in this design example, with its wide 10:1 frequency range, the potential output frequency error due to v set error alone ranges from less than 1% when v ctrl is at its minimum up to 36% when v ctrl is at its maximum. this error must be accounted for in the system design.
ltc6990 18 6990p applications information depending on the applications requirements, the non- inverting vco circuit in figure 13 may be preferred for this wide of a frequency variation as its maximum inac- curacy due to v set error is only 9% and can be reduced to only 3% with a small change to the voltage tuning range speci? cation. reducing v set error effects in vco applications figure 13 shows a vco that reduces the effect of v set by adding an op-amp to make v ctrl dependent on v set . this circuit also has a positive transfer function (the out- put frequency increases as v in increases). furthermore, for positive v in voltages, this circuit places the greatest absolute frequency error at the highest output frequency. compared to the simple vco circuit of figure 11, the absolute frequency error is unchanged. however, with the maximum absolute frequency error (in hertz) now occurring at the highest output frequency, the relative frequency error (in percent) is greatly improved. additionally, by choosing the vcos speci? cations shrewdly, the frequency error (in percent) due to v set variation is reduced to v set /v set = 3%. to realize this improve- ment, the design must abide by three conditions. first, the v in voltage must be positive throughout the range. second, choose v max /v min f max /f min . last, choose r vco /r set r4/r3. figure 13 shows a design similar to the previous design example where the v min voltage is now speci? ed to be 0.4v. this satis? es the v max /v min f max /f min condition and the design assures that the output frequency error due to v set variation is only 3%. figure 13. vco with reduced v set sensitivity 6990 f13 ltc6990 oe gnd set out v + div c1 0.1f r1 1m r2 280k divcode = 3 (n div = 8, hi-z = 0) r set 249k 3v r vco 75k C + 3v 3v 10khz to 100khz f out v ctrl v set 1/2 ltc6078 r4 30.1k c4 33pf r3 100k 0.4v to 4v v in f out 1m h z ? 5 0k 7 n div ?r vco ? r vco r set v in v set 1 | ? ? r4 r3 a ? ? 1 ? ? if r4 r3 r vco r set , the equation reduces to: f out = 1mhz ? 50k 7 n div ?r set ? v in v set v in ?25khz/v
ltc6990 19 6990p figure 14. digitally controlled oscillator with v set variation eliminated 6990 f14 ltc6990 oe gnd set out v + div c1 0.1f r1 r2 r set v + r vco C + v + 1/2 ltc6078 ltc1659 v + v cc ref gnd v out p d in clk cs /ld f out 1m h z ? 5 0k 7 n div ?r vco ?1 r vco r set d in 4096 | ? d in = 0 to 4095 eliminating v set error effects with dac frequency control many dacs allow for the use of an external reference. if such a dac is used to provide the v ctrl voltage, the v set error is eliminated by buffering v set and using it as the dacs reference voltage, as shown in figure 14. the dacs output voltage now tracks any v set variation and eliminates it as an error source. the set pin cannot be tied directly to the reference input of the dac because the current drawn by the dacs ref input would affect the frequency. i set extremes (master oscillator frequency extremes) pushing i set outside of the recommended 1.25a to 20a range forces the master oscillator to operate outside of the 62.5khz to 1mhz range in which it is most accurate. applications information the oscillator will still function with reduced accuracy in its extended range (see the electrical characteristics section). the ltc6990 is designed to function normally for i set as low as 1.25a. at approximately 500na, the oscillator output will be frozen in its current state. for n div = 1 or 2, out will halt in a low state. but for larger divider ratios, it could halt in a high or low state. this avoids introduc- ing short pulses while modulating a very low frequency output. note that the output will not be disabled as when oe is low (e.g. the output will not enter a high impedance state if hi-z = 1). at the other extreme, the master oscillator frequency can reach 2mhz for i set = 40a (r set = 25k). it is not recom- mended to operate the master oscillator beyond 2mhz because the accuracy of the div pin adc will suffer.
ltc6990 20 6990p applications information modulation bandwidth and settling time the ltc6990 will respond to changes in i set up to a C3db bandwidth of 0.4 ? f out (see figure 15). this makes it easy to stabilize a feedback loop around the ltc6990, since it does not introduce a low-frequency pole. settling time depends on the master oscillator frequency. following a 2x or 0.5x step change in i set , the output frequency takes approximately six master clock cycles (6 ? t master ) to settle to within 1% of the ? nal value. an example is shown in figure 16. power supply current the power supply current varies with frequency, supply voltage and output loading. it can be estimated under any condition using the following equation: i s(typ) v + ?f master ?7pf + v + ?f out ? (13pf + c load ) + v + 480k + v + 2?r load + 1.75 ?i set + 50a the equation is also valid for oe = 0 (output disabled), with f out = 0hz. figure 15. modulation frequency response figure 16. settling time f mod /f out (hz/hz) 0.1 $ f out (f mod )/ $ f out (dc) (db) 0 C20 C30 C10 C40 1 6990 f15 10 v ctrl = 0.536v + 0.278v ? sin(2?f mod ?t) f out =18.75khz 10% C3db at 0.4?f out r set = 200k r vco = 464k divcode = 4(16) 10s/div 6990 f16 v ctrl 2v/div f out 50khz/div out 2v/div v + = 3.3v, divcode = 0 r set = 200k, r vco = 464k f out = 175khz and 350khz
ltc6990 21 6990p 6990 f17 ltc6990 oe gnd set out v + div c1 0.1f r1 r2 r set v + v + div set out gnd oe c1 r1 r2 v + r set dcb package oe gnd set out v + div r2 v + r set tsot-23 package r1 c1 figure 17. supply bypassing and pcb layout applications information supply bypassing and pcb layout guidelines the ltc6990 is a 2.2% accurate silicon oscillator when used in the appropriate manner. the part is simple to use and by following a few rules, the expected performance is easily achieved. the most important use issues involve adequate supply bypassing and proper pcb layout. figure 17 shows example pcb layouts for both the sot-23 and dcb packages using 0603 sized passive components. the layouts assume a two layer board with a ground plane layer beneath and around the ltc6990. these layouts are a guide and need not be followed exactly. 1. connect the bypass capacitor, c1, directly to the v + and gnd pins using a low inductance path. the connection from c1 to the v + pin is easily done directly on the top layer. for the dcb package, c1s connection to gnd is also simply done on the top layer. for the sot-23, out can be routed through the c1 pads to allow a good c1 gnd connection. if the pcb design rules do not allow that, c1s gnd connection can be accomplished through multiple vias to the ground plane. multiple vias for both the gnd pin connection to the ground plane and the c1 connection to the ground plane are recommended to minimize the inductance. capacitor c1 should be a 0.1f ceramic capacitor. 2. place all passive components on the top side of the board. this minimizes trace inductance. 3. place r set as close as possible to the set pin and make a direct, short connection. the set pin is a current summing node and currents injected into this pin directly modulate the operating frequency. having a short connection minimizes the exposure to signal pickup. 4. connect r set directly to the gnd pin. using a long path or vias to the ground plane will not have a signi? cant affect on accuracy, but the direct, short connection is recommended and easy to apply. 5. use a ground trace to shield the set pin. this provides another layer of protection from radiated signals. 6. place r1 and r2 close to the div pin. a direct, short connection to the div pin minimizes the external signal coupling.
ltc6990 22 6990p typical applications full range vco with any n div setting (f max to f min for v in = 0v to v set ) 6990 ta03 ltc6990 5v oe gnd set out v + div c1 0.1f r1 r2 r set 826k 5v 5v d1 in4148 C + lt1490 r vco1 26.1k v in 0v to 1v r vco2 26.1k full range vco with any n div setting (positive frequency control, f min to f max for v in = 0v to v set 6990 ta04 ltc6990 5v oe gnd set out v + div c1 0.1f r1 r2 r set2 412k r set1 412k 5v 5v C + lt1490 r3 10k v in 0v to 1v r4 10k r vco 53.6k programming n div using an 8-bit dac 6990 ta02 ltc6990 oe gnd set out v + div c1 0.1f r set 619k 2.25v to 5.5v c2 0.1f p ltc2630-lz8 sdi sck cs /ld v cc gnd v out divcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dac code 0 24 40 56 72 88 104 120 136 152 168 184 200 216 232 255
ltc6990 23 6990p typical applications speaker alarm. modulate tone with r vco within 500hz to 8khz span 6990 ta05 ltc6990 oe gnd set out v + div 1m 887k 97.6k step ramp 5v 5v r vco 20k 5v 50k 8 2n2222 in4004 overvoltage detector/alarm. direct drive of piezo alarm 6990 ta06 ltc6990 5v 24v oe gnd set out v + div 1m piezo alarm 4khz murata pkm29-3a0 100k 523k 392k r b 10.7k r a 787k 5v 400mv C + lt6703-3 v alarm 400mv 1 r a r b | ? 30v 6990 ta07 ltc6990 5v oe gnd set out v + div 1m piezo alarm murata pkm29-340 f = 4khz 10k on off 523k 392k 5v direct piezo alarm driver. adjust frequency for maximum alarm sound pressure (maximum annoyance for best effect)
ltc6990 24 6990p typical applications isolated v f converter. v in provided by isolated measurement circuit. 5s rise/fall time of isolator limits f max to 60khz 6990 ta08 ltc6990 5v 365 3.3v oe gnd set out v + div 1m 523k 412 f out 157k v in 0v to 5v 75k 5v moc207m 6990 ta09 ltc6990 oe gnd set out v + div r1 1m 2k 1m sine cosine r2 280k 0.1f 4.12k 1m r set 49.9k r vco 267k freq adj 5v 5v C + ltc1440 out ref 1.18v hyst lt1004 C2.5v 2.5v 50/100 bp s1a n + C C lp clock ltc1059 or 1/2 ltc1060 s a/b v cc v + 5v agnd C + 10k 124k 5.11k 51.1k 2.5v 5v quadrature sine wave oscillator. voltage controlled frequency range from 2hz to 18khz with 1v p-p constant output amplitude
ltc6990 25 6990p typical applications 6990 ta10 ltc6990 oe gnd set out v + div 1m 523k 21.5k + 22k at 25c b = 3964 thermistor: vishay nths120601n2202j 5v f out 5v 60.4k temperature to frequency converter. 3% linearity from C20c (f out 20khz) to 75c (f out 25khz) 6990 ta11 ltc6990 oe gnd set out v + div 1m 681k 10k + 22k at 25c b = 3964 26k 5v f out 5v 100k 5v 10k 26k C + lt1490 thermistor: vishay nths120601n2202j full range temperature to frequency converter. 16khz to 1khz from C20c to 80c 6990 ta12 ltc6990 oe gnd set out v + div 187k 1m 619k sfh213 i pd 5v f out 5v 222k 5v 24.9k 1000pf C + lt1677 light to frequency converter. f out C1.4khz per microampere of photo diode current, i pd
ltc6990 26 6990p package description dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715) 3.00 p 0.10 (2 sides) 2.00 p 0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.115 typ r = 0.05 typ 1.35 p 0.10 (2 sides) 1 3 6 4 pin 1 bar top mark (see note 6) 0.200 ref 0.00 C 0.05 (dcb6) dfn 0405 0.25 p 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 s 45 o chamfer 0.25 p 0.05 1.35 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.70 p 0.05 3.55 p 0.05 package outline 0.50 bsc
ltc6990 27 6990p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 6 plcs (note 3) datum a 0.09 C 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc6990 28 6990p linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0510 ? printed in usa related parts part number description comments ltc1799 1mhz to 33mhz thinsot silicon oscillator wide frequency range ltc6900 1mhz to 20mhz thinsot silicon oscillator low power, wide frequency range ltc6906/ltc6907 10khz to 1mhz or 40khz thinsot silicon oscillator micropower, i supply = 35a at 400khz ltc6930 fixed frequency oscillator, 32.768khz to 8.192mhz 0.09% accuracy, 110s start-up time, 105a at 32khz typical application ultrasonic frequency sweep generator 6990 ta13 ltc6990 oe gnd set out v + div c1 0.1f r1 976k r2 102k r set1 49.9k r set2 750k c set 0.022f 2.25v to 5.5v f out = 500khz to 31.25khz oe 74hc125 sweeps from 500khz to 31.25khz in a few milliseconds (controlled by c set ).

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